First, the definition of a data hold time of a general synchronous circuit and its verification method will be described with reference to a block diagram of a sequential logic circuit shown in FIG. 1. As shown in FIG. 1, an external input IN is received by a combinational circuit 102, and outputted as an external output OUT. A storage element group 101 used with this combinational circuit 102 is supplied with a particular master clock MCK for driving the storage element group 101. Consider the testing of a timing specification of a synchronous circuit such as shown in FIG. 1. In this testing, it is necessary to check the timing specification, particularly of the so-called data setup time and data hold time with respect to the storage element group 101.
FIG. 2 is a particular example of a sequential logic circuit wherein a storage element group shown in FIG. 1 is replaced with flip-flops which are typical storage elements. As shown in FIG. 2, data from a first combinational circuit 103 is inputted to a data input terminal D of a D-type flip-flop (FFI) 106. The data output terminal Q of FFI 106 is coupled via a second combinational circuit 104 to the data input terminal D of a D-type flip-flop (FFII) 107. The data output terminal Q of FFII 107 is connected to a third combinational circuit 105. Master clocks MCK are supplied to the clock input terminals CK of FFI and FFII 106 and 107.
A verification of the timing specification of FFI and FFII 106 and 107 serving as storage elements, i.e., a verification of the data setup times and data hold times, will be discussed. The data setup times Tsetup and data hold times Thold definitely determined by FFI and FFII 106 and 107 themselves are shown in the timing chart of FIG. 3. Specifically, a signal D.sub.I supplied to the data input terminal D of the D-type flip-flop 106, 107 should be established at a time Ts led at least by the setup time Tsetup relative to the signal CK.sub.I supplied to the clock input terminal CK of the D-type flip-flop 106, 107. In addition, the data input D.sub.I should not change until a time Th delayed at least by the hold time Thold with respect to the clock input CK.
A verification of such timing specification for the whole of the synchronous circuit shown in FIG. 2 will be described. It is possible to verify a margin of a setup timing while changing the frequency of a synchronous clock signal. Namely, as the frequency of the clock signal is higher, the margin of the setup timing finally reaches a limit. At this limit, the data input D.sub.I to the flip-flop is established after the time Ts shown in FIG. 3. In this manner, the margin limit can be externally verified. On the contrary, it is not possible to externally verify the data hold time. The reason for this is as follows. For example, consider a verification of a data hold timing margin for the D-type flip-flop 107. In this case, data input to the data input terminal D of the D-type flip-flop 107 is synchronous with the master clock MCK. Therefore, even if the frequency of the clock signal is changed, the condition of the data hold time after the clock signal cannot be changed. This is the reason for verification inability.
The verification of a timing margin of data setup times and data hold times is very important to ensure the stable operation of a large scale synchronous logic circuit. Miniaturization techniques for large scale integrated logic circuits are advancing more and more. It is therefore becoming difficult to distribute synchronous clock signals at a high timing precision. This means that a skew of a clock signal is likely to occur among storage elements in a synchronous logic circuit. From the viewpoint of this or other reasons, it has been desired to carry out timing verification more reliably and correctly. Conventionally, however, since the verification method for the data hold time has not been provided, there has been a possibility of timing faults during mass production processes and in markets. Such timing faults inevitably lead again to circuit change and development, considerably affecting development scheduling and cost.
Furthermore, from the viewpoint of improving the function of such a scan flip-flop, it is desirable to make the input and output data changeable.